Verification of Digital Systems

• Explain the role of different tools and languages in digital system verification and their application in verification processes.
• Apply the basic theory of constrained random verification to academic and real-world situations, including principles of functional verification of RTL designs, state space exploration, transaction concepts, verification quality, and verification plans.
• Design directed and constrained random test cases, ensuring effective stimuli distribution to verify RTL designs for real-world situations.
• Implement and/or use functional checkers, reference models, scoreboards, and assertions using temporal logic to validate design correctness for real-world situations.
• Develop and apply coverage models and coverage model closure techniques to measure verification completeness.
• Implement testbenches in PyUVM using Python to verify the functionality of an RTL design.
• Use simulation tools to debug RTL designs, test cases, functional checks, and coverage models.
• Analyze the effectiveness of a verification environment by evaluating verification metrics and bug-finding capabilities.
• Integrate different verification components, including tests, checks, and coverage models, into a complete verification environment.
• Assess the final quality of a verification environment based on its ability to detect complex RTL design bugs.

Principles of verification of integrated circuits, constrained random verification, verification planning, transaction-based test bench architecture, coverage models, functional checks, assertions, PyUVM, Python tests, scoreboards, requirement-centric verification closure.

• 36 – 49 (Mon 8-12)

02139/02203, Basic skills in programming and digital electronics including some knowledge of a hardware description language.

Lectures, group work, and homework. Mandatory final project.

This course is given in collaboration with the company Syosil, which specializes in verification of digital systems.