Single-Course English 5 ECTS

Design of Digital Systems

Overall Course Objectives

To enable students to design larger digital circuits, e.g., hardware accelerators, in a systematic way and to implement these in FPGA technology using typical CAD tools (currently: VHDL and XILINX Vivado).

To enable students to analyze and optimize the speed and area of a given digital circuit.

Learning Objectives

  • Design a digital circuit that performs a given computation as a sequential circuit consisting of a finite state machine and a data-path.
  • Systematically pipeline a given circuit and identify errors in a given circuit where pipelining has been attempted.
  • Explain the performance parameters throughput and latency, explain the relationship between these and optimize the performance of a given circuit.
  • Analyze the timing-correctness of a given sequential circuit; possibly a circuit suffering from clock skew.
  • Explain the internal organization of a typical FPGA component (XILINX) and explain how its resources are best exploited when implementing a given circuit.
  • Explain how the a given VHDL-description syntesize to hardware (i.e., a structure of registers and combinational logic blocks) and estimate the hardware resources used for the implementation. Optimize the circuit by modifying the VHDL-code.
  • Explain the phenomenon “metastability” and describe how to correctly design a circuit comprising multiple clock domains.
  • Write efficient register transfer level VHDL code that synthesize to the intended circuit implementation.
  • Develop and apply testbenches for simulation and verification of the functional correctness of a digital circuit
  • Design complex digital circuits by stepwise refinement from a specification down to a level from which a hardware implementation can be synthesized.
  • Organize and plan the design of a larger digital circuit in a group comprising several students.
  • Document this work (design, implementation and test) in the form of a technical report addressing engineers in the field. The report must conform to usual requirements to form, content and level of abstraction.

Course Content

The course addresses the design of digital systems at the RT-level, the VHDL language, synthesis, and FPGA technology. The focus is on writing efficient RTL-code and on the relationship between VHDL-constructs and the corresponding synthesized hardware implementations.

Design of digital systems. Data-path and Control. Pipelining. From algorithm to a circuit. Performance measures (throughput and latency). The VHDL hardware description language. Simulation and synthesis. Introduction of FPGA technology. Design flow (specification, stepwise refinement, simulation, synthesis, implementation, and test). Timing analysis of sequential circuits; possibly circuits suffering from clock-skew.

A sequence of exercises supplements the lectures and provides hands-on experience using VHDL and the associated CAD tools. A small project concludes the course.

Recommended prerequisites

02139/02100/02102/02132, Basic skills in programming and digital electronics including some knowledge of VHDL (or another hardware description language).

Teaching Method

Lectures, exercises and project.



The course is a graduate-level course (for most students) or an upper-level undergraduate course (for some students with sufficient background in digital design).

See course in the course database.





13 weeks




DTU Lyngby Campus

Course code 02203
Course type Candidate
Semester start Week 35
Semester end Week 48
Days Thurs 8-12

7.500,00 DKK